Phd Position In CMOS Chip Design For State - space Models In LLM Acceleration

PhD Position in CMOS Chip Design

The Institute of Mechanical and Electrical Engineering at SDU invites applications for a 3-year PhD position in CMOS chip design for State-Space Models accelerators targeting edge-tasks and language models. This position is part of SDU's initiative to develop energy-efficient AI accelerators based on alternative model architectures that cannot be leveraged as efficiently on conventional computing platforms such as GPUs, CPUs and TPUs.

As language models become essential tools in society, there is a critical need to optimize their inference for edge and embedded systems. This project addresses that challenge through chip-level implementations of SSM architectures in advanced CMOS nodes, targeting latency- and energy-constrained environments.

Research area and project description

This project explores the use of state-space models (SSMs) for sequence modeling in large language models (LLMs), focusing on their CMOS-based hardware implementation. The PhD candidate will develop energy-efficient accelerator architectures by designing digital and mixed-signal blocks for SSM inference in edge-AI systems.

The successful candidate will explore novel SSM architectures that support sequence modeling in LLMs with a focus on mapping these models to hardware. The research will address:

• Mathematical formulation and architecture of SSMs for language tasks
• Energy-efficient implementation in CMOS (28nm or below)
• Hardware-aware modeling of state-space inference pipelines
• Simulation and synthesis of the architecture using EDA tools
• Benchmarking against transformer-based hardware accelerators

Work description

• Conduct a literature review on SSMs, LLM architectures, and hardware acceleration techniques.
• Investigating design choices that optimize the model across both the hardware and software stack.
• Design energy-efficient CMOS blocks implementing SSM-based LLMs.
• Prototype hardware blocks on FPGA and prepare for ASIC tape-out.
• Benchmark performance and comparison with transformer accelerators.
• Work with modeling tools and HDL simulators to validate functionality.
• Collaborate closely with algorithm designers to co-optimize architecture.
• Publish results in high-impact journals and conferences.

Qualifications

Applicants should hold a relevant MSc degree in electronics, electrical engineering, computer engineering, or related fields.

• Solid background in digital CMOS design and deep learning architectures.
• Add some more digital skills
• Experience with EDA tools such as Cadence Virtuoso, Spectre, or Mentor Graphics.
• Strong analytical and problem-solving skills, with the ability to work independently and in collaboration with multidisciplinary teams.
• Excellent verbal and written communication skills in English.

• Applicants should hold an MSc in electronics, computer engineering, or a closely related field.
• Knowledge on SSM algorithms,
• Hands-on experience with layout and tape-out of CMOS chips.
• Experience in AI chip prototyping and hardware-software co-design.
• Solid background in digital CMOS design, SSM algorithms, and deep learning architectures.

For further information, please contact Professor Farshad Moradi, moradi@sdu.dk or other members in the team (Associate professors Hooman Farkhani, Yasser Rezaeiyan, or Milad Zamani)

If you experience technical problems, please contact hcm-support@sdu.dk.

Application procedure

Before applying the candidates are advised to read the Faculty information for prospective PhD students and the SDU information on how to apply .

Assessment of the candidates is based on the application material, and an application must include:

• Motivated application.
• Curriculum Vitae.
• Master's and bachelor's degree certificates or equivalent, including transcripts of grades (copy of original/official English translation).
• Completed TEK PhD application form for 5+3 applicants. Find the form at the Faculty website.
• Completed TEK PhD form for calculation grade point average. Find the form at the Faculty website.
• An official document describing the grading scheme of the awarding universities (if not Danish).
• Only for applicants from programmes that evaluate thesis/examination project by approved/not approved: An official written assessment of the thesis or dissertation project from the grade giving institution. The statement must clearly state that the candidate has been among the top 30 pct. in the graduation class for the study programme.
• List of publications and maximum 2 examples of relevant publications (in case you have any publications).
• References may be included, you're welcome to use the form for reference letter at the Faculty website.
• A statement/documentation of other qualifications relevant to the position may also be included.

SUBMISSION GUIDE: Motivated application shall be uploaded as 'Cover letter' (max. 5 MB), Curriculum Vitae shall be uploaded as 'Resume' (max 5 MB). All other documents shall be uploaded as 'Miscellaneous documents' (max 10 files of max 50 MB per file).

All documents must be in English and PDF format. CPR number (civil registration no.) must be crossed out. All PDF-files must be unlocked and allow binding and may not be password protected.

The application deadline is September 15, 2025, at 11.59 PM / 23.59 (CET/CEST)

Applications will be assessed by an assessment committee. Shortlisting may be applied, and only shortlisted candidates will receive a written assessment. Interviews and tests may be part of the overall evaluation.

Appointment as a PhD fellow is a 3-year salaried position, and the monthly gross salary incl. pension is 36.138 DKK. If you have relevant postgraduate experience, you may be placed on a higher salary step.

The start date will be agreed with the successful candidate.

Applicants must hold a master's degree (equivalent to a Danish master's degree) at the time of enrollment and employment. Employment is contingent on enrollment approved by the PhD School. Enrollment will be in accordance with Faculty regulations and the Danish Ministerial Order on the PhD Programme at the Universities (PhD order). Employment will be in accordance with the collective agreement between the Ministry of Finance and the Danish Confederation of Professional Associations for academics in the state with the associated circular on the job structure for academic staff at Danish universities and the provisions for PhD fellows as described herein as well as the Protocol on PhD fellows signed by the Danish Ministry of Finance and the Danish Confederation of Professional Associations (AC).